Pdf optimized design of modified doubletail comparator. Samanehbabayanmashhadi and reza lotfi 20 1 proposed a high speed energy efficient double tail dynamic comparator. Analysis and design of a lowvoltage lowpower double tail comparator abstract. The cascaded double tail comparator is a high speed and a low power comparator and is most appropriate for the application. Gandhi and others published differential double tail dynamic cmos voltage comparator find, read and cite all the research you need on researchgate.
Implementation of high speed double tail comparator. Analysis and design of a lowvoltage lowpower double tail comparator introduction the comparator compares the voltages that appear at their inputs and outputs a voltage representing the sign of the net difference between them. This modification also results in considerable power savings when compared to the conventional dynamic comparator and double tail comparator between two inputs of a modern railtorail comparator is usually limited only by the full swing of power supply. Performance analysis and comparison of selfcalibrating dynamic comparator and advanced doubletail cmos dynamic comparators jasbir kaur1 nitin goyal 2 1 assistant professor 2 me vlsi 1,2pec university of technology chandigarh160012 abstractthis advanced doubletail dynamic comparator has two extra inverters which are inserted in the. By using this circuit we developed the level shifter circuit. Comparators have a crucial influence on the overall performance in high. The cadence virtuoso in an 180nm cmos process parameter is utilized in this design. Stdc is limited by high delay, more dynamic power consumption, large effect of kickback noise and large offset due to single tail current path. Final structure of the proposed double tail comparator.
Performance improvement of low power double tail comparator. Vlsi implementation of low power doubletail comparator using. The proposed comparator is designed based on the double tail architecture due to its better performance in the. Design of a double tail dynamic comparator for low power. The transient analysis behavior of the double tail comparator is demonstrated in figure 2. Pdf design and analysis of double tail comparator using. Keywordsdouble tail comparator,cross couple transistors,postive feedback,switching transistor. It is shown by time analysis and simulation that the delay time is significantly reduced compared to a conventional double tail latched comparator. Vlsi implementation of low power doubletail comparator. Design of new doubletail comparator with lowvoltage low. A single tail comparator has a transistor tail attached to its circuit with clock input.
Double tail comparator, dynamic clocked comparator, highspeed analogtodigital converters adcs, lowpower analog design, tanner eda tool 1. Adcs, require excessive speed, low power comparators with small chip area. The main idea of the modified comparator is to reduce the static power consumption by. Manikandan2 ece, student of pgp college of engineering and technology, india1 member of iste, ap, pgp college of engineering and technology, india2 abstractthe demand for high speed comparators will increase the efficient operations of adc architectures. Regenerative comparator, single tail comparator etc. Designing of double tail comparator for high speed.
During reset phase of comparator when clock is zero, the tail transistors are off. In this technique, increase the voltage difference between the output. Pdf analysis and design of a new modified doubletail. The double tail enables both a large current in the latching stage and wider mtail2, for f. Design has particularly focused on delay of double tail comparator, which are called clocked regenerative comparator. This modification also results in considerable power savings when compared to the conventional dynamic comparator and double tail comparator. Also comparators are the basic building elements for designing modern analog and mixed. Design and analysis of a lowvoltage doubletail comparator. Design and implementation of an 8bit double tail comparator. During the reset phase when clk 0 and m tail is off. Operation of the proposed comparator the operation of the proposed comparator is as follows see fig during reset phase clk 0, mtail1.
In the proposed dynamic double tail comparator system both the power dissipation and delay time would be significantly reduced. Transient simulations of the conventional double tail dynamic comparator for input voltage difference of 5 mv 2. It has less stacking and therefore it can operate at lower supply voltages. Power reduction in dynamic double tail comparator with cmos. Design and analysis of an ultralowpower doubletail latched. The proposed double tail comparator circuit has been verified and simulated using the spectre simulator from cadence. Analysis and design of a new modified doubletail comparator for.
For better performance of a double tail design in applications with low voltages, the suggested comparator is based on double tail architecture. Due to the better performance of double tail architecture in lowvoltage applications, samanehbabayan mashhadi and reza lotfi design incorporates double tail in its architecture. Design and analysis of double tail comparator using adiabatic. Keywords double tail comparator, dynamic clocked comparator, high speed analog to digital.
Pdf differential double tail dynamic cmos voltage comparator. The double tail architecture has two tail transistors hence the name is double tail comparator. Pdf one of the most important analog circuits required in many analog integrated circuits is comparator. Double tail comparator is a clocked regenerative comparator mostly used due to the ability of fast decisions making because of its strong positive feedback used in the regenerative latch. The structure of double tail dynamic comparator existing is based on this fact. Keywordsdoubletail comparator,cross couple transistors,postive feedback,switching transistor.
Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double tail comparator is modified for lowpower and fast operation even in small supply. Schematic diagram of the conventional double tail dynamic comparator 19. A new modified double tail comparator circuit is designed by applying adiabatic logic circuit and also by adding few switching transistors to dynamic double tail comparator circuit. Pdf implementation of high speed double tail comparator. Nowadays the comparators are most widely used in high speed applications such as analogtodigital converters which require high speed and low power. In this paper, a novel new double tail comparator which consumes very less power and can operate at the operation of the conventional dynamic comparator is. Vout vdd2 has to be obtained from an initial output voltage difference. In recent years, with the advance of wireless communication systems, microelectronics and sensor technologies, wireless sensor networks wsns are becoming a hotspot for scientific research and industrial applications. Design and analysis of double tail comparator using.
The intermediate nodes are charged to supply voltage. March 2014 design of double tail comparator for high speed adc. Hence the demand of high speed comparators with less delay and power is increasing. For the better performance of double tail architecture in low voltage applications the various comparator can be designed based on the doubletail structure. Design of double tail comparator for high speed adc s. Optimization and performance analysis of a lowvoltage high. Comparator was the basic building block of analog to digital comparator. Comparator is an important element in many data converter circuits, signal processing systems, such as telecommunication interfaces and in the sensory circuits. Double tail is derived from the fact that the comparator uses one tail for input stage and another tail for latching stage. In this technique, the voltage difference between the output nodes is. During this project, associate analysis on the delay. Design of a low voltage low power double tail comparator in.
Pdf on sep 30, 2017, hemlata gururani and others published design of 4bit flash adc using double tail comparator in nm technology find, read and cite all the research you need on researchgate. Its function is to compare two analog inputs and delivers a. Design and analysis of ultra highspeed lowpower double tail. Analysis and design of a new modified doubletail comparator.
Performance analysis and comparison of selfcalibrating. Performance of power consumption using doubletail comparator. But the power consumption is less and having high speed than conventional comparator figure. Double tail comparator is used for low power applications. Analysis and design of a lowvoltage lowpower doubletail. What is double tail in double tail dynamic comparator. The proposed comparator benefits from a positive feedback to achieve high resolution with low kickback noise. The single tail comparator is also known as conventional comparator. A high performance double tail comparator design using. Double tail comparator double tail architecture has two tail transistors. Design of high performance double tail comparator saranya p. Therefore, the double tail dynamic comparator dotdc is designed mainly to minimize delay and. In this paper, a new double tail comparator is proposed by modifying the low voltage low power double tail comparator circuit for power efficient and high speed operation.
Low voltage and high speed doubletail dynamic comparator. This topology has less stacking and therefore can operate at same supply voltages compared to the conventional dynamic comparator. S department of electronics and communication engineering, saintgits college of engineering, india abstract comparator is an important building blocks used in analogtodigital converters. A doubletail sense amplifier is presented here, which uses one tail for the input stage and another for the latching stage. Dec 21, 2016 transistor sizing is one of the most critical parts of comparator design which has a significant influence on comparator specifications.
Design and analysis of low power and high speed double tail. Based on the presented analysis, a new dynamic com parator is proposed, where the circuit of a conventional double tail comparator is modified for lowpower. Compared with the double tail comparator in the proposed comparator both the power consumption and delay time are substantially reduced. Design of a double tail dynamic comparator for low power and. Design of double tail comparator using finfetin 32nm technology. A regenerative comparator uses positive feedback to compare magnitude of two signals. This paper presents an optimum design of a double tail latch comparator based on transistor sizing with a great certainty to reach the best possible design due to using hspice as a software simulator linked with a heuristic algorithm. Pdf design of lowpower double tail dynamic comparator. Conventional double tail comparator a conventional double tail comparator is shown in fig 6 this topology has less stacking and therefore can operate. A high performance double tail comparator design using inverter stage parvathala swathi pg scholar department of ece vaagdevi engineering college bollikunta, warangal p. The conventional double tail comparator is modified. Design of double tail comparator using finfetin 32nm.
The performance of conventional dynamic comparators also called as single tail dynamic comparators i. Apr 04, 2016 this topology of dynamic comparators has less stacking and therefore can operate at lower supply voltages compared to the conventional dynamic comparator. The main motive behind the suggested comparator is to raise the vfnfp so that. The need for ultralowpower, space economical and high speed analogtodigital converters is pushing toward the utilization of dynamic regenerative comparators to maximize speed and power potency. W in double tail comparator using switching transistors with the same supply voltage. Analysis and design of a new modified doubletail comparator for high speed adc applications.
An analysis on the delay of dynamic comparators will be presented and analytical expressions are derived. As a result, circuit shows up to 40% low power consumption. A modern approach for low power dynamic double tail comparator doi. Design of a double tail dynamic comparator for low. Sep 11, 2015 this paper presents a new ultralow power double tail latched comparator suited for biomedical applications. Introduction comparators are mostly used in electronic components after operational amplifiers.
Design of low voltage and high speed double tail dynamic comparator for low power. As the proposed double tail comparator architecture shows better performance in low voltage applications, the modified comparator is designed based on the double tail structure. A modern approach for low power dynamic double tail comparator. Keywordsdouble tail comparator, dynamic clocked comparator, high speed analog to digital. Design of a single tail comparator on a 90nm technology. Low voltage and high speed double tail dynamic comparator by. Low voltage and high speed double tail dynamic comparator. The schematic diagram of the conventional single tail comparator is shown in figure 1. Power and delay analysis on doubletail comparator using nano. Design of level shifter circuit using double tail comparator. Power and delay of the modified comparators are analyzed for its application in high. Rajani assistant professor department of ece vaagdevi engineering college bollikunta, warangal abstract. The circuit design of a conventional comparator is modified with a double tail dynamic comparator to reduce the power and voltage by increasing the speed.
This comparator is used for low power applications. A comparator with no feedback which is called an op amp. The need for ultra lowpower, area efficient, and high speed analogtodigital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. Design of a double tail dynamic comparator for low power and high speed applications. Design of low voltage and high speed doubletail dynamic. Optimum design of a doubletail latch comparator on power. The conventional double tail regenerative comparator is modified using control transistors and nmos switches.
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